The present invention relates to digital signal processors having instruction pipelines, and more particularly an instruction pipeline which combines two or more instructions into a single control word which can be executed by one execution unit.
The Digital Signal Processor, DSP, is a specialized microprocessor known for its computational power which can process signal streams with complex mathematical formulas in real time. A DSP is typically ten to fifty times more powerful than typical microprocessor devices such as the microprocessor cores used in ASICs or microcontrollers. Applicant's ZSP DSP has an open architecture which allows it to be easily programmed and used for numerous applications.
DSPs achieve high performance in several ways. They normally include several execution units which may operate in parallel. In a single clock cycle a number of mathematical operations and load and store operations may be executed, or at least partially executed in the case of operations which require more than one clock cycle to complete. Use of an instruction pipeline is also a known method of increasing the effective speed of operation of a DSP. A pipeline separates an operation into multiple steps which are performed at separate stages of the pipeline. Each stage may be performing a part or subpart of a different operation, effectively allowing the processor to perform multiple operations in parallel. The applicant's ZSP DSP has four execution units, two for mathematical functions and two for loading and storing data. In a DSP having four execution units, the instruction pipeline may act like four pipelines. The pipeline can issue up to four instructions at the same time, one for each execution unit. However, the pipeline must confirm that instructions which are issued at the same time do not conflict, that is that they do not violate grouping or execution rules. For example, if instruction A is to operate on the result of instruction B, then instruction A cannot be executed until after instruction B. In that case, instruction A cannot be issued at the same time as instruction B. If two instructions require loading of data into the same register, they cannot be executed in the same clock cycle. A grouping stage is provided in such pipelines to compare multiple instructions to detect and prevent such conflicts. The grouping stage issues sets of instructions which can be properly executed at the same time. For maximum efficiency, a pipeline will simultaneously issue instructions to all execution units which are ready to accept a new instruction.
DSPs are commonly programmed with RISC, Reduced Instruction Set Computer, instructions. Typically these instructions have a limited fixed length, e.g. sixteen bits. While the limited length helps to simplify the programming process, the limited instruction length can also cause conflicts and produce inefficiency. For example loading of immediate data into a register may require two instructions because of instruction limitations. A single execution unit could perform the process if it is properly instructed.